In the fabrication of integrated circuit devices, logic products are often produced using salicide (self-aligned silicide) processes in order to obtain higher circuit performance. In silicidation, a refractory metal-containing layer is deposited and then annealed. The underlying silicon reacts with the refractory metal layer to produce a silicide overlying the source and drain regions. The silicided source/drain regions then can have lower resistance than non-silicided regions, especially in smaller geometries, and hence, higher circuit performance.
In order to shrink cell size and enhance performance of a device at a same time, a fin-shaped field effect transistor (FinFET) becomes one of the most important processes in the art. The manufacturing process of a conventional FinFET is much more complicated than a conventional planar field effect transistor. Also due to the complexity of the manufacturing process of the conventional FinFET, there are some defects produced and lowering product yield. For example, work function of a gate is tuned during a gate formation process; however, an annealing have to be performed for silicidation after the gate formation in order to form contacts, and it leads to a problem that work function is altered in the annealing due to thermal effect. Moreover, in any heating or annealing process, the complicated structure and different materials coexist on a same substrate resulting in uneven distribution and absorption of heat. In these cases, temperature of portions of the substrates rise slower during the annealing process or even cannot rise to the desired temperature, and it can cause hardware error or even shutdown. Product yield and productivity reduction and increasing cost become a subject and is needed to be improved.
Accordingly, the present invention provides a manufacturing method for tuning metal gate in order to solve above discussed issues.